Intel Core Ultra 300 Series "Panther Lake" Leaks: 16 CPU Cores, 12 Xe3 GPU Cores, and Five-Tile Package (2024)

Intel is preparing to launch its next generation of mobile CPUs with Core Ultra 200 series "Lunar Lake" leading the charge. However, as these processors are about to hit the market, leakers reveal Intel's plans for the next-generation Core Ultra 300 series "Panther Lake". According to rumors, Panther Lake will double the core count of Lunar Lake, which capped out at eight cores. There are several configurations of Panther Lake in the making based on the different combinations of performance (P) "Cougar Cove," efficiency (E) "Skymont," and low power (LP) cores. First is the PTL-U with 4P+0E+4LP cores with four Xe3 "Celestial" GPU cores. This configuration is delivered within a 15 W envelope. Next, we have the PTL-H variant with 4P+8E+4LP cores for a total of 16 cores, with four Xe3 GPU cores, inside a 25 W package. Last but not least, Intel will also make PTL-P SKUs with 4P+8E+4LP cores, with 12 Xe3 cores, to create a potentially decent gaming chip with 25 W of power.

Intel's Panther Lake CPU architecture uses an innovative design approach, utilizing a multi-tile configuration. The processor incorporates five distinct tiles, with three playing active roles in its functionality. The central compute operations are handled by one "Die 4" tile with CPU and NPU, while "Die 1" is dedicated to platform control (PCD). Graphics processing is managed by "Die 5", leveraging Intel's Xe3 technology. Interestingly, two of the five tiles serve a primarily structural purpose. These passive elements are strategically placed to achieve a balanced, rectangular form factor for the chip. This design philosophy echoes a similar strategy employed in Intel's Lunar Lake processors. Panther Lake is poised to offer greater versatility compared to its Lunar Lake counterpart. It's expected to cater to a wider range of market segments and use cases. One notable advancement is the potential for increased memory capacity compared to Lunar Lake, which capped out at 32 GB of LPDDR5X memory running at 8533 MT/s. We can expect to hear more potentially at Intel's upcoming Innovation event in September, while general availability of Panther Lake is expected in late 2025 or early 2026.

View at TechPowerUp Main Site | Source

AleksandarK said:

One notable advancement is the potential for increased memory capacity compared to Lunar Lake, which capped out at 32 GB of LPDDR5X memory running at 8533 MT/s.

Click to expand...

How the actual f*ck do you ship a product limited to 32GB in this day and age, especially when your previous products have supported 128GB or more? Lunar Lake seems like even more of a prototype than MTL was.

Assimilator said:

How the actual f*ck do you ship a product limited to 32GB in this day and age, especially when your previous products have supported 128GB or more? Lunar Lake seems like even more of a prototype than MTL was.

Click to expand...

On-package memory for Lunar Lake. Designed for ultrathin portables where 16GB/32GB is absolutely OK, there are still plenty of 8GB mobile devices out there. At last count Intel are claiming 8 million MTL laptops sold with sales being restricted by CPU packaging capacity. No sales figures from AMD as yet. AMD reports its Q2 2024 financial results on July 30, there may be some information then.

pressing on said:

On-package memory for Lunar Lake. Designed for ultrathin portables where 16GB/32GB is absolutely OK, there are still plenty of 8GB mobile devices out there. At last count Intel are claiming 8 million MTL laptops sold with sales being restricted by CPU packaging capacity. No sales figures from AMD as yet. AMD reports its Q2 2024 financial results on July 30, there may be some information then.

Click to expand...

In limiting the amount of system ram to 32GB, it will automatically limit the target market. Most people are fine with 16 or 32GB of system RAM, but there will always be users that may need more for their workflow. Like for Apple, the system RAM is soldered, but you can tell they cater to the different markets by allowing > 32GB of system ram for a price.

Wirko said:

What's the LPDDR5X bus width (or total bandwidth) of the Lunar Lake? Intel makes it clear as mud, and tech sites don't all agree. I believe it has two 32-bit channels.

Click to expand...

According to the TechPowerUp article 'Intel Lunar Lake-MX SoC with On-Package LPDDR5X Memory Detailed' of November 20 2023 "...Depending on the processor model, the memory sizes on offer will be either 16 GB or 32 GB, across a 160-bit dual-channel (4x sub-channel) interface".

pressing on said:

According to the TechPowerUp article 'Intel Lunar Lake-MX SoC with On-Package LPDDR5X Memory Detailed' of November 20 2023 "...Depending on the processor model, the memory sizes on offer will be either 16 GB or 32 GB, across a 160-bit dual-channel (4x sub-channel) interface".

Click to expand...

Yes, I saw that. It's probably wrong because it assumes 4 x 32-bit (plus ECC). Indeed, one of the slides does state this: Capacity: 16GB (16Gb,1R,x64)-32GB (16Gb,2R,2x64). But to me, "2x64" just means 2 ranks on the same 64-bit bus.

A newer TPU article has a slide with more exact info: Support for 16b x4 channels. In comparison, Apple too has 16-bit LPDDR non-X controllers on the M3 series (eight of them on the plain M3). That's why I think it's 64 bits total. Not even 80 because ECC is unlikely in this segment.

watzupken said:

In limiting the amount of system ram to 32GB, it will automatically limit the target market. Most people are fine with 16 or 32GB of system RAM, but there will always be users that may need more for their workflow. Like for Apple, the system RAM is soldered, but you can tell they cater to the different markets by allowing > 32GB of system ram for a price.

Click to expand...

Lunar Lake isn't intended for those markets like for professional video editors that require huge ammounts of RAM. In fact, 32GB is more than enough even for a good portion of professional users.

As for Apple, they don't actually sell all kind of configurations. A M3 Mackbook pro can be configured to be 8GB, 16GB or 24GB, for you to get more than that, you need at least a M3 Pro which caps at 36GB, and for those who want even beyond that, they need to get a M3 Max.

Lunar Lake isn't there to compete with M3 Max and similar chips, by the time you need that much memory you would probably be more disgruntled towards the 4P+0E+4LPE cores.

N/A said:

it's a quad core no HT, efficiency and Lp cores can be discarded as filler, still I have to admit 12 of them are faster than my 14 core Xeon. those take only 2mm2 per core L2cache included or 24mm2. And you probably don't need more than 32GB with that.

Click to expand...

Skymont cores in Lunarlake are better than Raptor Cove cores in 14900K. It is in no way a filler, and a key advantage in achieving great battery life according to Intel engineers.

The next E cores are on their way to completely make the P core design obsolete in about 2 years.

Wirko said:

A newer TPU article has a slide with more exact info: Support for 16b x4 channels. In comparison, Apple too has 16-bit LPDDR non-X controllers on the M3 series (eight of them on the plain M3). That's why I think it's 64 bits total. Not even 80 because ECC is unlikely in this segment.

Click to expand...

And they can put two of them for 128-bits, just like every CPU generation since Pentium 4 went dual channel in 2003. LPDDR having subdivisions confuse people endlessly, but Intel laptops have been using them for a decade now and has always been 128-bits. Whether you call 1x128 or 2x64 or 128x1 it doesn't matter, because in the end it's always 128-bits.

DavidC1 said:

Skymont cores in Lunarlake are better than Raptor Cove cores in 14900K. It is in no way a filler, and a key advantage in achieving great battery life according to Intel engineers.

The next E cores are on their way to completely make the P core design obsolete in about 2 years.

Click to expand...

I'd rather say that both designs will join into one but yeah, agreed, that seems quite likely to me too. Still, there's a third type (LP), a cut down E, and that one will remain a separate design for ultra-low power.

DavidC1 said:

And they can put two of them for 128-bits, just like every CPU generation since Pentium 4 went dual channel in 2003.

Click to expand...

Can, but didn't this time. Again, that's my understanding.

DavidC1 said:

LPDDR having subdivisions confuse people endlessly, but Intel laptops have been using them for a decade now and has always been 128-bits. Whether you call 1x128 or 2x64 or 128x1 it doesn't matter, because in the end it's always 128-bits.

Click to expand...

Always 128 bits of LPDDR, are you sure about that? Some lower end thin laptops only have single-channel DDR (not LPDDR) memory, soldered down and not expandable.

DavidC1 said:

Skymont cores in Lunarlake are better than Raptor Cove cores in 14900K. It is in no way a filler, and a key advantage in achieving great battery life according to Intel engineers.

The next E cores are on their way to completely make the P core design obsolete in about 2 years.

And they can put two of them for 128-bits, just like every CPU generation since Pentium 4 went dual channel in 2003. LPDDR having subdivisions confuse people endlessly, but Intel laptops have been using them for a decade now and has always been 128-bits. Whether you call 1x128 or 2x64 or 128x1 it doesn't matter, because in the end it's always 128-bits.

Click to expand...

There are no indications at all Intel is ditching P cores. Nova Lake is still 2.5 years away and is still using them. Maybe when we see rentable units we will see a unified core design, but nothing is known about that that's been leaked.

DavidC1 said:

Skymont cores in Lunarlake are better than Raptor Cove cores in 14900K. It is in no way a filler, and a key advantage in achieving great battery life according to Intel engineers.

Click to expand...

They are about the same or a bit better than Raptor Cove at the same clock and as part of the ring bus

DavidC1 said:

The next E cores are on their way to completely make the P core design obsolete in about 2 years.

Click to expand...

I think for some segments absolutely. If you are doing < 10W SoCs, then all E cores design makes sense.

Those E cores aren't that little cores like we think of A53s, A55 or similar, they are still huge cores and are really only little when compared to the massive cove or zen cores.

To put it into perspective, a Skymont core has about the same vector throughput as Zen 2/3/4(i.e. 4x128b vectors per cycle vs 2x256b vectors per cycle).

persondb said:

They are about the same or a bit better than Raptor Cove at the same clock and as part of the ring bus

Click to expand...

We shall take that with a grain of salt. One Skymont vs. one Raptor Cove core, yes; but what about four Skymont vs. four Raptor Cove cores? The former sit in clusters of four and share some resources.

persondb said:

they are still huge cores and are really only little when compared to the massive cove or zen cores

Click to expand...

Yes, that's true even when compared to Zen 4c cores.

Wirko said:

We shall take that with a grain of salt. One Skymont vs. one Raptor Cove core, yes; but what about four Skymont vs. four Raptor Cove cores? The former sit in clusters of four and share some resources.

Click to expand...

That is true, but there were however some improvements in regard to that, notably the bigger L2 and the double bandwidth from L2.

Each skymont core can pull off 64B/cycle from L2 and the L2 can service in total 128B/cycle. Which is better than Gracemont as that was 64B/cycle in Gracemont and would help a lot with resource contention. It's still ofc not as good as a four different cores which each has their individual L2 and the bandwidth is entirely theirs.

It can also help that they now have L1 to L1 transfers from the same cluster, without needing to go into L3. This could help when you have a cluster working into a workload that shares a lot of modified data between threads.

persondb said:

That is true, but there were however some improvements in regard to that, notably the bigger L2 and the double bandwidth from L2.

Each skymont core can pull off 64B/cycle from L2 and the L2 can service in total 128B/cycle. Which is better than Gracemont as that was 64B/cycle in Gracemont and would help a lot with resource contention. It's still ofc not as good as a four different cores which each has their individual L2 and the bandwidth is entirely theirs.

It can also help that they now have L1 to L1 transfers from the same cluster, without needing to go into L3. This could help when you have a cluster working into a workload that shares a lot of modified data between threads.

Click to expand...

Plus, sharing resources is not only a bad thing. It means that, in a purely 1T workload, a single thread has access to four times the L2 cache otherwise available to it.

I think the raptor cove big cores have like 3MB L2? and the GRT cores in Raptor Lake have 4MB (same for arrow lake it sounds like), so a single thread from arrow lake would have a 4MB L2 to potentially access. And if Intel were to pursue e-cores as a main microarchitecture, they could always beef up the L2 cache even further to give them more punch.

chrcoluk said:

Really feels like Intel are pumping out CPUs way too often now, I feel like I have read about 3-4 different unreleased generations of Intel chips on here in the past couple of weeks.

Click to expand...

I don't think they're doing it more often than they need to. Intel this year has Lunar Lake and Arrow Lake. AMD this year has Ryzen AI (their Lunar Lake counterpart) and their Ryzen desktop parts (which do seem to differ as they don't have the Ryzen AI NPU). AMD also has Ryzen 5x3D coming whenever. Intel next year has Panther Lake. AMD might have nothing, or they might have the 5x3D depending on when it comes out. Personally, if Panther Lake is a new microarchitecture, I'd take that over nothing.

Wirko said:

Always 128 bits of LPDDR, are you sure about that? Some lower end thin laptops only have single-channel DDR (not LPDDR) memory, soldered down and not expandable.

Click to expand...

Single channel designs always existed. And "single channel" means 64-bits, not 16-bits as LPDDR or 32-bit as DDR5 terminologies use. That's my point.

Minus Infinity said:

There are no indications at all Intel is ditching P cores. Nova Lake is still 2.5 years away and is still using them. Maybe when we see rentable units we will see a unified core design, but nothing is known about that that's been leaked.

Click to expand...

The P cores 3-4 years away will have to use a completely different design, perhaps adopting a larger version of the E, or even the farther off ones like the RU. The design and even the team based on the current P core will be ditched, just like the "P core" went from Netburst in 2003 to Core in 2006.